1.3 君正T31+IMX307网络模组
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<h1>一、芯片参数</h1>
<h3>1. CPU</h3>
<h5>1.1 XBurst®-1 core</h5>
<p>– XBurst® FPU instruction set supporting both single and double floating point format which are IEEE754 compatible
– XBurst® 9-stage pipeline micro-architecture, the operating frequency is 1.5GHz
· MMU
– 32-entry joint-TLB
– 8 entry instruction TLB
– 8 entry data TLB</p>
<p>· L1 Cache
– 32kB instruction cache
– 32kB data cache
· Hardware debug support
· 16kB tight coupled memory
· L2 cache
– 128kB unify cache</p>
<h5>1.2 Video Processor Unit</h5>
<p>· Support DVT HEVC/AVC/JPEG Encoder
· Support HEVC up to 20Mbit/s and AVC up to 40Mbit/s, maximum frame rate is 1920x1080@60fps or 2592x1900@25fps
· maximum size up to 2592X4096 resolution</p>
<h5>1.3 Image Signal Processor</h5>
<p> Dynamic/Static Defect Pixel Correction
Green Equalization
Black Level Correction
Lens Shading Correction
3A(Auto Exposure/White Balance/Focus)
Support Statistical Information Output(3A)
Adaptive Dynamic Range Compression
Demosaic
Sharpen Sharpen
Bayer Denoise
2D/3D Denosie
Color Noise Suppression
Lens Distortion Correction
2D Color Correction
3D Color Correction
Gamma Correction
Defog, WDR
3 Independent Image Scaler and Output
Crop, Mirror and Flip
Support Maximum Resolution: 2592X2048</p>
<h5>1.4 Smart LCD Controller</h5>
<p> Basic Features Basic Features Basic Features Basic Features
― Display size up to 800x600@60Hz,24BPP
― Smart LCD interface 6800(type A) and 8080(type B)
Color Supports
― Support up to 16,777,216 (16M) colors
Panel Supports
― transmit 565 by one cycle via SLCD 16bit data interface
― transmit 666 by two cycle via SLCD 9bit data interface
― transmit 565 by two cycle via SLCD 8bit data interface
― transmit 888 by three cycle via SLCD 8bit data interface
― Supports different size of display panel
― Supports internal DMA operation and direct write register operation</p>
<h5>1.5 Video input</h5>
<p> Support 8/10/12 bit RGB Bayer input
Support DVP,BT1120 (serial mode)/BT656/BT601 and MIPI CSI(2 lane up to 1.5Gbps)
Support maximum: 2592x1900@25fps
Support single-sensor input</p>
<h5>1.6 Audio System</h5>
<p> Integrated Audio codec
– 24 bits DAC with 93dB SNR
– 24 bits ADC with 92dB SNR
– Supportsignal-ended and differential microphone input and line input
– Automatic Level Control (ALC) for smooth audio recording
– Pure logic process: no need for mixed signal layers and less mask cost
– Programmable input and output analog gains
– Digital interpolation and decimation filter integrated
– Sampling rate 8K/12K/16K/24K/32/44.1K/48K/96KI</p>
<h5>1.7 Memory Interface</h5>
<p> Integrated 1G bit DDR on chip
Static memory interface
– Support Support 6 external chip selection CS6~1#. Each bank can be configured separately
– The size and base address of static memory banks are programmable
– Direct interface to 8-bit bus width external memory interface devices or external static memory to each bank. Read/Write strobe setup time and hold periods can be programmed and inserted in an access cycle to enable connection to low-speed memory
– Wait insertion by WAIT pin
– Automatic wait cycle insertion to prevent data bus collisions in case of consecutive memory accesses to different banks, or a read access followed by a write memory accesses to the same bank</p>
<h5>1.8 System Functions</h5>
<p> Clock generation and power management
– On-chip 12/24/48MHZ oscillator circuit
– One three-chip phase-locked loops (PLL) with programmable multiplier
– CCLK, HHCLK, H2CLK, PCLK, H0CLK, DDR_CLK, VPU_CLK frequency can be changed separately for software by setting registers
– SSI clock supports 50M clock
– MSC clock supports 100M clock
– Functional-unit clock gating
– Shut down power supply for P0, ISP, VPU, IPU
Timer and counter unit with PWM output and/or input edge counter
– Provide eight separate channels, six of them have input signal transition edge counter
– 16 -bit A counter and 16-bit B counter with auto-reload function every channel
– Support interrupt generati when the A counter underflow
– Three clock sources: RTCLK (real time clock), EXCLK (external clock input),PCLK APB Bus clock)selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected
– Every channel has PWM output
OS timer controller
– 64-bit counter and 32-bit compare register
– Support interrupt generation when the counter matches the compare register
– Two clock sources: RTCLK (real time clock), HCLK (system bus clock) selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected
Interrupt controller
– Total 64 interrupt sources
– Each interrupt source can be independently enabled
– Priority mechanism to indicate highest priority interrupt
– All the registers are accessed by CPU
– Unmasked interrupts can wake up the chip in sleep mode
– Another set of source, mask and pending registers to serve for PDMA</p>
<p> Watchdog timer
– Generates WDT reset
– A 16-bit Data register and a 16-bit counter
– Counter clock uses the input clock selected by software</p>
<p> PCLK, EXTAL and RTCCLK can be used as the clock for counter</p>
<p> The division ratio of the clock can be set to 1, 4, 16, 64, 256 and 1024 by software</p>
<p> Direct memory access controllers
– Support up to 32 independent DMA channels
– Descriptor or No-Descriptor Transfer mode compatible with previous JZ SoC
– Transfer data units: 1-byte, 2-byte, 4 byte, 4-byte, 16-byte, 32-byte, 64-byte, 128-byte
– Transfer number of data unit: 1 ~ 2^24-1
– Independent source and destination port width: 8-bit, 16-bit, 32-bit
– Fixed three priorities of channel groups: 0~3, highest; 4~11: mid; 12~31: lowest
– An extra INTC IRQ can be bound to one programmable DMA channel</p>
<p> SAR A/D Controller
– 1Channels
– Resolution: 10-bit
– Integral nonlinearity: ±1 LSB
– Differential nonlinearity: ±0.5 LSB
– Resolution/speed: up to 2MSPS
– Max Frequency: 24MHz
– Low power dissipation: 1.5 mW(worst)
– Support multi-touch detect
– Support write control command by software
– Single-end and Differential Conversion Mode
– Support external touch screen controller
– Pin Description</p>
<p> OTP Slave Interface
– Total 1024 bits. Lower 192bits are read only, other higher bits are read-able and write-able</p>
<h5>1.9 Peripherals</h5>
<p> General -Purpose I/O ports
– Each port can be configured as an input, an output or an ernate function port
– Each port can be configured as an interrupt source of low/high level or rising/falling edge triggering. Every interrupt source can be masked independently
– Each port has an internal pull-up pull-down resistor connected. The pull-up/down resistor can be disabled
– GPIO output 3 interrupts, each interrupt corresponds to the group, to INTC</p>
<p> SMB Controller SMB Controller SMB Controller
– Two-wire SMB serial interface – consists of a serial data line (SDA) and a serial clock (SCL)
– Two speeds
– Standard mode (100 Kb/s)
– Fast mode (400 Kb/s)
– Device clock is identical with pclk
– Programmable SCL generator
– Master or slave SMB operation
– 7-bit addressing/10-bit addressing
– 16-level transmit and receive FIFOs
– Interrupt operation
– The number of devices that you can connect to the same SMB-bus is limited only by the maximum bus capacitance of 400pF
– APB interface
– 2 independent SMB channels (SMB0，SMB1)</p>
<p> One High Speed Synchronous serial interfaces(SFC)
– 3 protocols support: National’s Microwire, TI’s SSP, and Motorola’s SPI
– transmit-only or receive-only operation
– MSB first for command and data transfer, and LSB first for address transfer
– 64 entries x 32 bits wide data FIFO
– one device select
– Configurable sampling point for reception
– Configurable timing parameters: tSLCH, tCHSH and tSHSL
– Configurable flash address wide are supported
– transfer formats: Standard SPI only
– two data transfer mode: slave mode and DMA mode
– Configurable 6 phases for software flow</p>
<p> Normal Speed Synchronous serial interfaces (SSI1)
– 3 protocols support: National’s Microwire, TI’s SSP, and Motorola’s SPI 3 protocols
– Full-duplex or transmit-only or receive-only operation
– Programmable transfer order: MSB first or LSB first
– 128 entries deep x 32 bits wide transmit and receive data FIFOs
– Configurable normal transfer mode or Interval transfer mode
– Programmable clock phase and polarity for Motorola’s SSI format
– Back-to-back character transmission/reception mode
– Loop back mode for testing</p>
<p> Three UARTs (UART0, UART1, UART2)
– Full-duplex operation
– 5-, 6-, 7- or 8-bit characters with optional no parity or even odd parity and with 1, 1½, or 2 stop bits
– 64x8 bit transmit FIFO and 64x11bit receive FIFO
– Independently controlled transmit, receive (data ready or timeout), line status interrupts
– Internal diagnostic capability Loopback control and break, parity, overrun and framing-error is provided
– Separate DMA requests for transmit and receive data services in FIFO mode
– Supports modem flow control by software or hardware
– Slow infrared asynchronous interface that conforms to IrDA specification</p>
<p> Two MMC/SD/SDIO controllers(MSC0, MSC1)
– Fully compatible with the MMC System Specification version 4.2
– Support SD Specification 3.0
– Support SD I/O Specification 1.0 with 1 command channel and 4 data channels
– Consumer Electronics Advanced Transport Architecture (CE-ATA – version 1.1)
<strong>– Maximum data rate is 50MBps</strong>
– Support MMC data width 1bit ,4bit and 8bit
– Built-in programmable frequency divider for MMC/SD bus
– Built-in Special Descriptor DMA
– Maskable hardware interrupt for SDIO interrupt, internal status and FIFO tatus
– 128 x 32 built-in data FIFO
– Multi-SD function support including multiple I/O and combined I/O and memory
– IRQ supported enable card to interrupt MMC/SD controller
– Single or multi block access to the card including erase operation
– Stream access to the MMC card
– Supports SDIO read wait, interrupt detection during 1-bit or 4-bit access
– Supports CE-ATA digital protocol commands
– Support Command Completion Signal and interrupt to CPU
– Command Completion Signal disable feature
– The maximum block length is 4096bytes</p>
<p> USB 2.0 USB interface
– Complies with the USB 2.0 standard for high-speed (480 Mbps) functions and with the On-The-Go supplement to the USB 2.0 specification
– Operates either as the function controller of a high-/full-speed USB peripheral or as the host/peripheral in point-to-point or multi-point communications with other USB functions
– Supports Session Request Protocol (SRP) and Host Negotiation Protocol(HNP)
– UTMI+ Level 3 Transceiver Interface
– Soft connect/disconnect
– 16 Endpoints
– Dedicate FIFO
– Supports control, interrupt, ISO and bulk transfer</p>
<p> Ethernet Media Access controller and interface
– 10, 100Mbps data transfer rates with the following PHY interfaces:
RMII interface to communicate with an external Fast Ethernet PHY
– Full -duplex operation:
IEEE 802.3x flow control automatic transmission of zero-quanta Pause frame on flow control input de-assertion
forwarding of received Pause frames to the user application
– Half-duplex operation:
– CSMA/CD Protocol support
– Frame bursting and frame extension in 100 Mbps half-duplex operation
– Preamble and start of frame data (SFD) insertion in Transmit path
– Preamble and SFD deletion in the Receive path
– Automatic CRC and pad generation controllable on a per-frame basis frame basis
– Automatic Pad and CRC Stripping options for receive frames
– Flexible address filtering modes, such as:
Up to 31 additional 48-bit perfect(DA) address filters with masks for each byte
64 -bit Hash filter for multicast and unicast (DA) addresses
Option to pass all multicast addressed frames
Promiscuous mode to pass all frames without any filtering for network monitoring
Pass all incoming packets (as per filter) with a status report
– Support Standard or Jumbo Ethernet frames with up to 2KB of size
– IEEE 802.1Q VLAN tag detection for reception frames
– MDIO master interface for PHY device configuration and management
– CRC replacement, Source Address field insertion or replacement, and VLAN insertion, replacement, and deletion in transmitted frames with pe-frame control
– Programmable watchdog timeout limit in the receive path
– Detect remote wake-up frames and AMD magic</p>
<p> Digital True Random Number Generator（DTRNG）
– Pure digital logic circuits
– True random number
– Interrupt mode and no interrupt mode</p>
<h5>1.10 Bootrom</h5>
<pre><code>16KB Boot ROM memory</code></pre>
<h1>二、接口线路图</h1>
<p>＊ 12V 供电+百兆网络（8pin）<em>1
<img src="http://showdoc.xstrive.com/server/index.php?s=/api/attachment/visitFile/sign/b6ccc1b270a30e70e3494babad496287&amp;showdoc=.jpg" alt="" />
＊ 串口调试接口（3pin）</em>1
<img src="http://showdoc.xstrive.com/server/index.php?s=/api/attachment/visitFile/sign/5ac1e4a841b5f277bf9333169118976f&amp;showdoc=.jpg" alt="" />
＊ 模拟音频输入+模拟音频输出+TTL串口1+USB接口+GPIO+IRCUT检测（12pin）<em>1
<img src="http://showdoc.xstrive.com/server/index.php?s=/api/attachment/visitFile/sign/b10a08d9d35982539b74472027234a0f&amp;showdoc=.jpg" alt="" />
主板对应接线图
<img src="http://showdoc.xstrive.com/server/index.php?s=/api/attachment/visitFile/sign/af9bd2735c855254472b347ce920cfe4&amp;showdoc=.jpg" alt="" />
＊ Micro SD卡插槽</em>1
<img src="http://showdoc.xstrive.com/server/index.php?s=/api/attachment/visitFile/sign/b9dedcbbce7ff654d43a915aab8f6e26&amp;showdoc=.jpg" alt="" />
＊ IRCUT接口*1
<img src="http://showdoc.xstrive.com/server/index.php?s=/api/attachment/visitFile/sign/b5d96bf314386379de400957e88112e5&amp;showdoc=.jpg" alt="" /></p>
<h1>三、常见问题解答</h1>
<table>
<thead>
<tr>
<th style="text-align: left;">问题</th>
<th style="text-align: left;">答案</th>
</tr>
</thead>
<tbody>
<tr>
<td style="text-align: left;">1、焦距是多少？</td>
<td style="text-align: left;">开发板焦距随机发货的，批量采购才定镜头焦距，可选2.4mm/4mm/6mm</td>
</tr>
<tr>
<td style="text-align: left;">2、对应的镜头焦距呢？不同的镜头有不同的isp参数吧？</td>
<td style="text-align: left;">2.8 4 6 ISP参数都调了的</td>
</tr>
<tr>
<td style="text-align: left;">3、提供ISP源码吗？</td>
<td style="text-align: left;">君正的isp没有源码，isp君正已经调好了的</td>
</tr>
<tr>
<td style="text-align: left;">4、T31跑的是linux系统吧，支持触摸屏？</td>
<td style="text-align: left;">是Linux系统，不支持触摸屏幕</td>
</tr>
<tr>
<td style="text-align: left;">5、有烧录器？</td>
<td style="text-align: left;">直接串口网络烧录就可以的</td>
</tr>
<tr>
<td style="text-align: left;">6、带的开发环境能否支持摄像头快速启动部分的资源？需要做二次的摄像头拍照功能开发。所以需要快速启动和截图功能的驱动？</td>
<td style="text-align: left;">没有哦，快启只支持定制开发，有对应的调试接口，有SDK需要自己适配</td>
</tr>
<tr>
<td style="text-align: left;">7、基础开发环境和基础功能例程你有么？</td>
<td style="text-align: left;">有的</td>
</tr>
<tr>
<td style="text-align: left;">8、提供什么样的资料？提供H265编码，和RTSP源码吗？</td>
<td style="text-align: left;">提供SDK虚拟机， 没有rtsp源码，有265编码例子</td>
</tr>
<tr>
<td style="text-align: left;">9、支持远程唤醒功能吗?</td>
<td style="text-align: left;">不支持</td>
</tr>
<tr>
<td style="text-align: left;">10、这个开发板摄像头是外置的吗？</td>
<td style="text-align: left;">内置的，装个镜头即可</td>
</tr>
<tr>
<td style="text-align: left;">11、有usb数据传输口吗？</td>
<td style="text-align: left;">扩展接口那里有USB</td>
</tr>
<tr>
<td style="text-align: left;">12、畸变矫正怎么操作？ 在设置菜单里面调用吗？</td>
<td style="text-align: left;">畸变矫正是君正官方的功能， SDK里面有</td>
</tr>
<tr>
<td style="text-align: left;">13、虚拟机密码是什么？这个嵌入式系统中root密码是多少？ 这个t31zx有cpu手册吗？看看内部有哪些资源</td>
<td style="text-align: left;">虚拟机密码：123456， root是空密码，SDK里面有手册</td>
</tr>
<tr>
<td style="text-align: left;">14、t31相比t40有哪些差距？</td>
<td style="text-align: left;">T40支持智能分析，T31不支持，T40才有NPU算力</td>
</tr>
<tr>
<td style="text-align: left;">15、T31支持双目吗？</td>
<td style="text-align: left;">不支持</td>
</tr>
<tr>
<td style="text-align: left;">16、这款支持x1500开发吗？</td>
<td style="text-align: left;">不支持</td>
</tr>
<tr>
<td style="text-align: left;">17、君正的开发板用的方式接wifi？usb还是sdio？ wifi芯片用什么？</td>
<td style="text-align: left;">usb， T31+imx307不能加4G和wifi模块，T31+GC4653可以另外加4G和wifi模块，WiFi芯片用的8188，加wifi模块+50元</td>
</tr>
<tr>
<td style="text-align: left;">18、里面的固件能否更改? 里面的网络模型是server还是client？ 定制怎么收费？ 曝光参数能否单独设置？ 硬件能定制吗？定制费用，包含软件吗？ 有没有基础的sdk？</td>
<td style="text-align: left;">固件可以定制； rtsp的server；定制收费需要根据您的需求评估；曝光参数能单独设置；硬件可以定制；定制费不包含软件源码，可以调驱动； 有基础的SDK</td>
</tr>
<tr>
<td style="text-align: left;">19、你们可以定制方案吗？比如用T31的，有配套的APP和服务器吗？</td>
<td style="text-align: left;">可以定制方案，配套的APP也可以定制</td>
</tr>
<tr>
<td style="text-align: left;">20、服务器是要租用吗？是怎么样的方式提供？</td>
<td style="text-align: left;">服务器按流量计费，按您自己的需求，一般定制的客户是自己架设服务器</td>
</tr>
<tr>
<td style="text-align: left;">21、提供手机端APP源码范例吗？</td>
<td style="text-align: left;">没有APP源码哦</td>
</tr>
<tr>
<td style="text-align: left;">22、提供uboot Linux内核呢？</td>
<td style="text-align: left;">提供的</td>
</tr>
<tr>
<td style="text-align: left;">23、开发板的ip 是192.168.0.10吗，怎么ping不通？</td>
<td style="text-align: left;">您需要自己烧写固件，里面默认是测试固件</td>
</tr>
<tr>
<td style="text-align: left;">24、这个摄像头能耐多少度高温？</td>
<td style="text-align: left;">80度</td>
</tr>
<tr>
<td style="text-align: left;">25、支持USB读取T卡数据吗？</td>
<td style="text-align: left;">支持读取TF卡数据，有插 TF卡的位置</td>
</tr>
<tr>
<td style="text-align: left;">26、支持mipi吗？</td>
<td style="text-align: left;">支持的</td>
</tr>
<tr>
<td style="text-align: left;">27、Linux系统的具体版本是什么？flash多大？</td>
<td style="text-align: left;">linux版本：4.4.49 ，此版本包在sdk中有，flash： nor flash 大小：16M</td>
</tr>
<tr>
<td style="text-align: left;">28、flash 16M，跑完摄像机demo后可用空间还有多少呢？</td>
<td style="text-align: left;">官方提供的uboot大小 250以内，kernel -2M以内，文件系统2-3M, 其他的就是你可以使用的空间了，demo程序编译出来是很小的</td>
</tr>
<tr>
<td style="text-align: left;">29、支持自动曝光，自动白平衡吗？</td>
<td style="text-align: left;">不支持，板子支持但是sensor不支持，原来的sensor是贴在板子上所以需要定制硬件。</td>
</tr>
<tr>
<td style="text-align: left;">30、可以做到200ms稳定图像输吗?</td>
<td style="text-align: left;">这个是开发板，开发板的性能跟您自己写的软件有关的。如果需要测试性能建议直接买我们的摄像头成品</td>
</tr>
<tr>
<td style="text-align: left;">31、资料里面有提供GB28181的代码吗？</td>
<td style="text-align: left;">没有的呢</td>
</tr>
<tr>
<td style="text-align: left;">32、包含原理图和PCB吗？</td>
<td style="text-align: left;">不包含，原理图和PCB是单独付费的，一起8000</td>
</tr>
<tr>
<td style="text-align: left;">33、可以和另一个板子串口通信吗？</td>
<td style="text-align: left;">可以的，有一个调试串口</td>
</tr>
<tr>
<td style="text-align: left;">34、这个开发板支持root？提供root密码吗？</td>
<td style="text-align: left;">支持的，提供</td>
</tr>
<tr>
<td style="text-align: left;">35、扩展接口 可以同时支持 麦克风、喇叭、pwm、两个gpio吗？</td>
<td style="text-align: left;">其他都是可以的，但是只支持一个gpio</td>
</tr>
<tr>
<td style="text-align: left;">36、有SLCD显示屏接口吗？</td>
<td style="text-align: left;">没有的呢</td>
</tr>
<tr>
<td style="text-align: left;">37、有linux的源码？</td>
<td style="text-align: left;">sdk里面有linux内核源码</td>
</tr>
</tbody>
</table>