1.2 T31+GC4653 400W camera
<table>
<thead>
<tr>
<th style="text-align: left;">400W Camera</th>
</tr>
</thead>
<tbody>
<tr>
<td style="text-align: left;">Type</td>
<td style="text-align: center;">Name</td>
<td>Specific Parameter</td>
</tr>
<tr>
<td style="text-align: left;">Name model</td>
<td style="text-align: center;">Chip</td>
<td>IngenicT31ZX</td>
</tr>
<tr>
<td style="text-align: left;">Sensor</td>
<td style="text-align: center;">GalaxyCore GC4653</td>
</tr>
<tr>
<td style="text-align: left;">Acquisition Parameter</td>
<td style="text-align: center;">Lens</td>
<td>4mm (Optional 2.8mm,6mm,8mm and other lenses, suitable for different installation scenarios</td>
</tr>
<tr>
<td style="text-align: left;">Sensor type</td>
<td style="text-align: center;">GC4653 1/2.7'' 4MP sensor</td>
</tr>
<tr>
<td style="text-align: left;">Minimum illumination</td>
<td style="text-align: center;">0.01lux/F1.2(colors) 0.01lux/F1.2(black)</td>
</tr>
<tr>
<td style="text-align: left;">Shutter</td>
<td style="text-align: center;">1/3 second to 1/100.000 second</td>
</tr>
<tr>
<td style="text-align: left;">Day-night conversion</td>
<td style="text-align: center;">Support hard light sensitive soft light sensitive</td>
</tr>
<tr>
<td style="text-align: left;">Video Parameter</td>
<td style="text-align: center;">Video compression standard</td>
<td>H.264/H.265</td>
</tr>
<tr>
<td style="text-align: left;">Compress the output bitrate</td>
<td style="text-align: center;">128Kbps~8000Kbps</td>
</tr>
<tr>
<td style="text-align: left;">Number of streams</td>
<td style="text-align: center;">dual-stream</td>
</tr>
<tr>
<td style="text-align: left;">Maximum image size</td>
<td style="text-align: center;">2560x1440</td>
</tr>
<tr>
<td style="text-align: left;">Maximum frame rate</td>
<td style="text-align: center;">25FPS</td>
</tr>
<tr>
<td style="text-align: left;">Image setting</td>
<td style="text-align: center;">Brightness, contrast, saturation, exposure, upside down, left and right mirror</td>
</tr>
<tr>
<td style="text-align: left;">Audio parameter</td>
<td style="text-align: center;">audio output</td>
<td>support</td>
</tr>
<tr>
<td style="text-align: left;">Audio input</td>
<td style="text-align: center;">support</td>
</tr>
<tr>
<td style="text-align: left;">Network</td>
<td style="text-align: center;">access protocol</td>
<td>HTTP-FLV/RTSP/WEBRTC/RTMP/WS-FLV/WS-RAW/ONVIF GB/T28181</td>
</tr>
<tr>
<td style="text-align: left;">Networking protocol</td>
<td style="text-align: center;">Support for TCP/IP, DHCP, DNS, NTP, RTSP, RTMP live</td>
</tr>
<tr>
<td style="text-align: left;">Wired network</td>
<td style="text-align: center;">1 RJ45 10M/100M Ethernet port</td>
</tr>
<tr>
<td style="text-align: left;">Function</td>
<td style="text-align: center;">Local client</td>
<td>support</td>
</tr>
<tr>
<td style="text-align: left;">Network access</td>
<td style="text-align: center;">support</td>
</tr>
<tr>
<td style="text-align: left;">Local upgrade</td>
<td style="text-align: center;">support</td>
</tr>
<tr>
<td style="text-align: left;">OSD superposition</td>
<td style="text-align: center;">Supports more than 2 user-defined regions Time display</td>
</tr>
<tr>
<td style="text-align: left;">Storage</td>
<td style="text-align: center;">TF</td>
<td>Supports up to 512GBSD card storage</td>
</tr>
<tr>
<td style="text-align: left;">Video download</td>
<td style="text-align: center;">Supports local and remote video download</td>
</tr>
<tr>
<td style="text-align: left;">Replay</td>
<td style="text-align: center;">Supports remote video playback</td>
</tr>
<tr>
<td style="text-align: left;">Else</td>
<td style="text-align: center;">Operating temperature and humidity</td>
<td>The humidity ranges from -10 ° C to 50 ° C and is less than 95%</td>
</tr>
<tr>
<td style="text-align: left;">TDP</td>
<td style="text-align: center;">3W MAX</td>
</tr>
</tbody>
</table>
<p><img src="http://showdoc.xstrive.com/server/index.php?s=/api/attachment/visitFile&amp;sign=02919c9e1ebbf83098497a97efd75ca4" alt="" /></p>
<h1>1、Chip parameter</h1>
<h3>1. CPU</h3>
<h5>1.1 XBurst®-1 core</h5>
<p>– XBurst® FPU instruction set supporting both single and double floating point format which are IEEE754 compatible
– XBurst® 9-stage pipeline micro-architecture, the operating frequency is 1.5GHz
· MMU
– 32-entry joint-TLB
– 8 entry instruction TLB
– 8 entry data TLB</p>
<p>· L1 Cache
– 32kB instruction cache
– 32kB data cache
· Hardware debug support
· 16kB tight coupled memory
· L2 cache
– 128kB unify cache</p>
<h5>1.2 Video Processor Unit</h5>
<p>· Support DVT HEVC/AVC/JPEG Encoder
· Support HEVC up to 20Mbit/s and AVC up to 40Mbit/s, maximum frame rate is 1920x1080@60fps or 2592x1900@25fps
· maximum size up to 2592X4096 resolution</p>
<h5>1.3 Image Signal Processor</h5>
<p> Dynamic/Static Defect Pixel Correction
Green Equalization
Black Level Correction
Lens Shading Correction
3A(Auto Exposure/White Balance/Focus)
Support Statistical Information Output(3A)
Adaptive Dynamic Range Compression
Demosaic
Sharpen Sharpen
Bayer Denoise
2D/3D Denosie
Color Noise Suppression
Lens Distortion Correction
2D Color Correction
3D Color Correction
Gamma Correction
Defog, WDR
3 Independent Image Scaler and Output
Crop, Mirror and Flip
Support Maximum Resolution: 2592X2048</p>
<h5>1.4 Smart LCD Controller</h5>
<p> Basic Features Basic Features Basic Features Basic Features
― Display size up to 800x600@60Hz,24BPP
― Smart LCD interface 6800(type A) and 8080(type B)
Color Supports
― Support up to 16,777,216 (16M) colors
Panel Supports
― transmit 565 by one cycle via SLCD 16bit data interface
― transmit 666 by two cycle via SLCD 9bit data interface
― transmit 565 by two cycle via SLCD 8bit data interface
― transmit 888 by three cycle via SLCD 8bit data interface
― Supports different size of display panel
― Supports internal DMA operation and direct write register operation</p>
<h5>1.5 Video input</h5>
<p> Support 8/10/12 bit RGB Bayer input
Support DVP,BT1120 (serial mode)/BT656/BT601 and MIPI CSI(2 lane up to 1.5Gbps)
Support maximum: 2592x1900@25fps
Support single-sensor input</p>
<h5>1.6 Audio System</h5>
<p> Integrated Audio codec
– 24 bits DAC with 93dB SNR
– 24 bits ADC with 92dB SNR
– Supportsignal-ended and differential microphone input and line input
– Automatic Level Control (ALC) for smooth audio recording
– Pure logic process: no need for mixed signal layers and less mask cost
– Programmable input and output analog gains
– Digital interpolation and decimation filter integrated
– Sampling rate 8K/12K/16K/24K/32/44.1K/48K/96KI</p>
<h5>1.7 Memory Interface</h5>
<p> Integrated 1G bit DDR on chip
Static memory interface
– Support Support 6 external chip selection CS6~1#. Each bank can be configured separately
– The size and base address of static memory banks are programmable
– Direct interface to 8-bit bus width external memory interface devices or external static memory to each bank. Read/Write strobe setup time and hold periods can be programmed and inserted in an access cycle to enable connection to low-speed memory
– Wait insertion by WAIT pin
– Automatic wait cycle insertion to prevent data bus collisions in case of consecutive memory accesses to different banks, or a read access followed by a write memory accesses to the same bank</p>
<h5>1.8 System Functions</h5>
<p> Clock generation and power management
– On-chip 12/24/48MHZ oscillator circuit
– One three-chip phase-locked loops (PLL) with programmable multiplier
– CCLK, HHCLK, H2CLK, PCLK, H0CLK, DDR_CLK, VPU_CLK frequency can be changed separately for software by setting registers
– SSI clock supports 50M clock
– MSC clock supports 100M clock
– Functional-unit clock gating
– Shut down power supply for P0, ISP, VPU, IPU
Timer and counter unit with PWM output and/or input edge counter
– Provide eight separate channels, six of them have input signal transition edge counter
– 16 -bit A counter and 16-bit B counter with auto-reload function every channel
– Support interrupt generati when the A counter underflow
– Three clock sources: RTCLK (real time clock), EXCLK (external clock input),PCLK APB Bus clock)selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected
– Every channel has PWM output
OS timer controller
– 64-bit counter and 32-bit compare register
– Support interrupt generation when the counter matches the compare register
– Two clock sources: RTCLK (real time clock), HCLK (system bus clock) selected with 1, 4, 16, 64, 256 and 1024 clock dividing selected
Interrupt controller
– Total 64 interrupt sources
– Each interrupt source can be independently enabled
– Priority mechanism to indicate highest priority interrupt
– All the registers are accessed by CPU
– Unmasked interrupts can wake up the chip in sleep mode
– Another set of source, mask and pending registers to serve for PDMA</p>
<p> Watchdog timer
– Generates WDT reset
– A 16-bit Data register and a 16-bit counter
– Counter clock uses the input clock selected by software</p>
<p> PCLK, EXTAL and RTCCLK can be used as the clock for counter</p>
<p> The division ratio of the clock can be set to 1, 4, 16, 64, 256 and 1024 by software</p>
<p> Direct memory access controllers
– Support up to 32 independent DMA channels
– Descriptor or No-Descriptor Transfer mode compatible with previous JZ SoC
– Transfer data units: 1-byte, 2-byte, 4 byte, 4-byte, 16-byte, 32-byte, 64-byte, 128-byte
– Transfer number of data unit: 1 ~ 2^24-1
– Independent source and destination port width: 8-bit, 16-bit, 32-bit
– Fixed three priorities of channel groups: 0~3, highest; 4~11: mid; 12~31: lowest
– An extra INTC IRQ can be bound to one programmable DMA channel</p>
<p> SAR A/D Controller
– 1Channels
– Resolution: 10-bit
– Integral nonlinearity: ±1 LSB
– Differential nonlinearity: ±0.5 LSB
– Resolution/speed: up to 2MSPS
– Max Frequency: 24MHz
– Low power dissipation: 1.5 mW(worst)
– Support multi-touch detect
– Support write control command by software
– Single-end and Differential Conversion Mode
– Support external touch screen controller
– Pin Description</p>
<p> OTP Slave Interface
– Total 1024 bits. Lower 192bits are read only, other higher bits are read-able and write-able</p>
<h5>1.9 Peripherals</h5>
<p> General -Purpose I/O ports
– Each port can be configured as an input, an output or an ernate function port
– Each port can be configured as an interrupt source of low/high level or rising/falling edge triggering. Every interrupt source can be masked independently
– Each port has an internal pull-up pull-down resistor connected. The pull-up/down resistor can be disabled
– GPIO output 3 interrupts, each interrupt corresponds to the group, to INTC</p>
<p> SMB Controller SMB Controller SMB Controller
– Two-wire SMB serial interface – consists of a serial data line (SDA) and a serial clock (SCL)
– Two speeds
– Standard mode (100 Kb/s)
– Fast mode (400 Kb/s)
– Device clock is identical with pclk
– Programmable SCL generator
– Master or slave SMB operation
– 7-bit addressing/10-bit addressing
– 16-level transmit and receive FIFOs
– Interrupt operation
– The number of devices that you can connect to the same SMB-bus is limited only by the maximum bus capacitance of 400pF
– APB interface
– 2 independent SMB channels (SMB0，SMB1)</p>
<p> One High Speed Synchronous serial interfaces(SFC)
– 3 protocols support: National’s Microwire, TI’s SSP, and Motorola’s SPI
– transmit-only or receive-only operation
– MSB first for command and data transfer, and LSB first for address transfer
– 64 entries x 32 bits wide data FIFO
– one device select
– Configurable sampling point for reception
– Configurable timing parameters: tSLCH, tCHSH and tSHSL
– Configurable flash address wide are supported
– transfer formats: Standard SPI only
– two data transfer mode: slave mode and DMA mode
– Configurable 6 phases for software flow</p>
<p> Normal Speed Synchronous serial interfaces (SSI1)
– 3 protocols support: National’s Microwire, TI’s SSP, and Motorola’s SPI 3 protocols
– Full-duplex or transmit-only or receive-only operation
– Programmable transfer order: MSB first or LSB first
– 128 entries deep x 32 bits wide transmit and receive data FIFOs
– Configurable normal transfer mode or Interval transfer mode
– Programmable clock phase and polarity for Motorola’s SSI format
– Back-to-back character transmission/reception mode
– Loop back mode for testing</p>
<p> Three UARTs (UART0, UART1, UART2)
– Full-duplex operation
– 5-, 6-, 7- or 8-bit characters with optional no parity or even odd parity and with 1, 1½, or 2 stop bits
– 64x8 bit transmit FIFO and 64x11bit receive FIFO
– Independently controlled transmit, receive (data ready or timeout), line status interrupts
– Internal diagnostic capability Loopback control and break, parity, overrun and framing-error is provided
– Separate DMA requests for transmit and receive data services in FIFO mode
– Supports modem flow control by software or hardware
– Slow infrared asynchronous interface that conforms to IrDA specification</p>
<p> Two MMC/SD/SDIO controllers(MSC0, MSC1)
– Fully compatible with the MMC System Specification version 4.2
– Support SD Specification 3.0
– Support SD I/O Specification 1.0 with 1 command channel and 4 data channels
– Consumer Electronics Advanced Transport Architecture (CE-ATA – version 1.1)
<strong>– Maximum data rate is 50MBps</strong>
– Support MMC data width 1bit ,4bit and 8bit
– Built-in programmable frequency divider for MMC/SD bus
– Built-in Special Descriptor DMA
– Maskable hardware interrupt for SDIO interrupt, internal status and FIFO tatus
– 128 x 32 built-in data FIFO
– Multi-SD function support including multiple I/O and combined I/O and memory
– IRQ supported enable card to interrupt MMC/SD controller
– Single or multi block access to the card including erase operation
– Stream access to the MMC card
– Supports SDIO read wait, interrupt detection during 1-bit or 4-bit access
– Supports CE-ATA digital protocol commands
– Support Command Completion Signal and interrupt to CPU
– Command Completion Signal disable feature
– The maximum block length is 4096bytes</p>
<p> USB 2.0 USB interface
– Complies with the USB 2.0 standard for high-speed (480 Mbps) functions and with the On-The-Go supplement to the USB 2.0 specification
– Operates either as the function controller of a high-/full-speed USB peripheral or as the host/peripheral in point-to-point or multi-point communications with other USB functions
– Supports Session Request Protocol (SRP) and Host Negotiation Protocol(HNP)
– UTMI+ Level 3 Transceiver Interface
– Soft connect/disconnect
– 16 Endpoints
– Dedicate FIFO
– Supports control, interrupt, ISO and bulk transfer</p>
<p> Ethernet Media Access controller and interface
– 10, 100Mbps data transfer rates with the following PHY interfaces:
RMII interface to communicate with an external Fast Ethernet PHY
– Full -duplex operation:
IEEE 802.3x flow control automatic transmission of zero-quanta Pause frame on flow control input de-assertion
forwarding of received Pause frames to the user application
– Half-duplex operation:
– CSMA/CD Protocol support
– Frame bursting and frame extension in 100 Mbps half-duplex operation
– Preamble and start of frame data (SFD) insertion in Transmit path
– Preamble and SFD deletion in the Receive path
– Automatic CRC and pad generation controllable on a per-frame basis frame basis
– Automatic Pad and CRC Stripping options for receive frames
– Flexible address filtering modes, such as:
Up to 31 additional 48-bit perfect(DA) address filters with masks for each byte
64 -bit Hash filter for multicast and unicast (DA) addresses
Option to pass all multicast addressed frames
Promiscuous mode to pass all frames without any filtering for network monitoring
Pass all incoming packets (as per filter) with a status report
– Support Standard or Jumbo Ethernet frames with up to 2KB of size
– IEEE 802.1Q VLAN tag detection for reception frames
– MDIO master interface for PHY device configuration and management
– CRC replacement, Source Address field insertion or replacement, and VLAN insertion, replacement, and deletion in transmitted frames with pe-frame control
– Programmable watchdog timeout limit in the receive path
– Detect remote wake-up frames and AMD magic</p>
<p> Digital True Random Number Generator（DTRNG）
– Pure digital logic circuits
– True random number
– Interrupt mode and no interrupt mode</p>
<h5>1.10 Bootrom</h5>
<pre><code>16KB Boot ROM memory</code></pre>
<h1>2、Interface diagram</h1>
<p>＊ 12V power + 100 Megabit network (8pin) <em>1
<img src="http://showdoc.xstrive.com/server/index.php?s=/api/attachment/visitFile/sign/b6ccc1b270a30e70e3494babad496287&amp;showdoc=.jpg" alt="" />
＊ Serial debugging port (3pin) </em>1
<img src="http://showdoc.xstrive.com/server/index.php?s=/api/attachment/visitFile/sign/5ac1e4a841b5f277bf9333169118976f&amp;showdoc=.jpg" alt="" />
＊ Analog audio input + analog audio output +TTL serial port 1+USB interface +GPIO+IRCUT detection (12pin) <em>1
<img src="http://showdoc.xstrive.com/server/index.php?s=/api/attachment/visitFile/sign/b10a08d9d35982539b74472027234a0f&amp;showdoc=.jpg" alt="" />
＊ The mainboard corresponds to the wiring diagram
<img src="http://showdoc.xstrive.com/server/index.php?s=/api/attachment/visitFile/sign/af9bd2735c855254472b347ce920cfe4&amp;showdoc=.jpg" alt="" />
＊ MicroSD card slot </em>1
<img src="http://showdoc.xstrive.com/server/index.php?s=/api/attachment/visitFile/sign/b9dedcbbce7ff654d43a915aab8f6e26&amp;showdoc=.jpg" alt="" />
＊ IRCUT interface *1
<img src="http://showdoc.xstrive.com/server/index.php?s=/api/attachment/visitFile/sign/b5d96bf314386379de400957e88112e5&amp;showdoc=.jpg" alt="" /></p>
<h1>三、Device FAQ</h1>
<table>
<thead>
<tr>
<th style="text-align: left;">Question</th>
<th style="text-align: left;">Answer</th>
</tr>
</thead>
<tbody>
<tr>
<td style="text-align: left;">1、Does this module support quick-start？</td>
<td style="text-align: left;">Not supported Oh only sdk, you need to adapt yourself</td>
</tr>
<tr>
<td style="text-align: left;">2、Can this module support TF card function for video recording storage?</td>
<td style="text-align: left;">support</td>
</tr>
</tbody>
</table>